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aikaoladexuanwei
轩卫
5 年前
trueaikaoladexuanwei


process(RST, CLK)
begin
if RST = '1' then
clock <= "00";
flags <= "0000000000000000";
elsif CLK'event and CLK = '1' then
case clock is

when "00" =>
inputA <=input;
clock <= "01";
when "01" =>
INPUTB <=input;
CLOCK <= "10";
when "10" =>
op <=input;
CLOCK <= "10";
case op is
WHEN "0000000000000000" => --ADD加
temp_Y <= inputA + inputB;
if(inputA(15) = '0' and inputB(15) = '0' and temp_Y(15) = '1') then --进行溢出和是否进位判断
flags<="0000000000000001";
end if;
if(inputA(15)='1' and inputB(15)='1' and temp_Y(15)='0') then --进行溢出和是否进位判断
flags<="0000000000000011";
end if;
if(temp_Y = "0000000000000000") then --0标志位与0进行比较
flags<= flags or "0000000000000100";
end if;
if(temp_Y(15) = '1') then --通过符号位来判断正负标志位
flags<=flags or "0000000000001000";
end if;

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下一条:
entity alu is Port ( CLK : in STD_LOGIC; RST : in STD_LOGIC; INPUT : in STD_LOGIC_VECTOR (15 downto 0); OUTPUT : out STD_LOGIC_VECTOR (15 downto 0); flag : out STD_LOGIC_VECTOR (15 downto 0) );end alu;architecture Behavioral of alu issignal clock : std_logic_vector(1 downto 0);signal inputA,inputB,op, temp_Y: std_logic_vector(15 downto 0); -- oprand a and b, function output to y.signal flags : std_logic_vector(15 downto 0);begin
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