entity alu is
Port ( CLK : in STD_LOGIC;
RST : in STD_LOGIC;
INPUT : in STD_LOGIC_VECTOR (15 downto 0);
OUTPUT : out STD_LOGIC_VECTOR (15 downto 0);
flag : out STD_LOGIC_VECTOR (15 downto 0)
);
end alu;

architecture Behavioral of alu is

signal clock : std_logic_vector(1 downto 0);
signal inputA,inputB,op, temp_Y: std_logic_vector(15 downto 0); -- oprand a and b, function output to y.
signal flags : std_logic_vector(15 downto 0);

begin