#脉冲同步器（快到慢）

原理图就是：最左端的数据选择器和寄存器，组成了快时钟域下的翻转电路；中间的两个寄存器是两级同步器；最后一个寄存器和异或门组成边沿检测电路。

`timescale 100ps/100ps

module pulse_detect(
input clka ,
input clkb ,
input rst_n ,
input sig_a ,

output sig_b
);
reg Q_sig_a;
always @(posedge clka or negedge rst_n) begin
if(~rst_n) begin
Q_sig_a <= 'd0;
end
else if(sig_a)begin
Q_sig_a <= ~Q_sig_a;
end
else if(~sig_a)begin
Q_sig_a <= Q_sig_a;
end
end
reg Q_buff0;
reg Q_buff1;
always @(posedge clkb or negedge rst_n) begin
if(~rst_n) begin
Q_buff0 <= 'd0;
Q_buff1 <= 'd0;
end
else begin
Q_buff0 <= Q_sig_a;
Q_buff1 <= Q_buff0;
end
end
reg Q_slow;
always @(posedge clkb or negedge rst_n) begin
if(~rst_n) begin
Q_slow <= 'd0;
end
else begin
Q_slow <= Q_buff1;
end
end

assign sig_b = Q_buff1 ^ Q_slow;

endmodule